1. Field of the invention
The present invention concerns a cell behaving like a linear capacitor when embedded in a network of MOS transistors exploited as linear pseudo-conductances.
1. Description of the prior art
In many applications of integrated circuits, and in particular of those using the CMOS technology, it may be beneficial to integrate resistive and capacitive components showing linear behavior. One particular application of this kind, to which the invention is by no means limited, is that of circuits used in artificial retinas for detecting contrasts and more particularly the edge contrasts of an object being examined.
In an article published in "Electronic Letters" of Feb. 4, 1993, Vol. 29, N.degree.3, pages 297 and 298, E. A. Vittoz and X. Arreguit describe a technique for synthesizing CMOS technology analog circuits to create linear resistive arrays that are made up exclusively of CMOS transistors and that are remarkable compact. Linear resistive circuits of the above kind can be used in digital/analog converters, current mode spatial filters, in particular for analyzing images captured by an artificial retina and other analogous circuit systems.
These linear resistive arrays are based on the following considerations.
The channel current of an MOS transistor biased in weak inversion (subthreshold regime) can be defined by the following equation: EQU I.sub.ds =g*.multidot.(V.sub.d * -V.sub.s *) (1)
where g* is defined as follows: ##EQU1## and V.sub.d * and V.sub.s * are the transforms of the drain voltage V.sub.d and the source voltage V.sub.s in accordance with the function: ##EQU2##
Hereinafter g* will be called the "pseudo-conductance" and V* will be called the "pseudo-voltages".
The following terms are used in the above equations.
______________________________________ I.sub.ds transistor source-drain current; g* transistor pseudo-conductance; V.sub.d * drain pseudo-voltage relative to local substrate (substrate or well) V.sub.s * source pseudo-voltage relative to local substrate (substrate or well); I.sub.S specific current proportional to a ratio between the width and the length of the transistor; V.sub.O arbitrary scaling voltage; V.sub.G transistor gate voltage relative to the local substrate (substrate or well); V.sub.TO transistor threshold voltage; n slope factor; U.sub.T thermodynamic potential; and V* pseudo-voltage of the node materialized by a transistor terminal (its source or its drain). ______________________________________
For more details of the above synthesis technique reference may be made to the article mentioned above, what it is essential to retain being that, as can be seen from equation (1) above, the behavior of the transistor can be analyzed using a pseudo-Ohms law, g* characterizing the pseudo-conductance of the transistor. It can also be seen that the technique in question can simplify and optimize the design and the topology of a resistive array formed of MOS transistors.
A drawback that until now has limited the use of integrated circuits based on the above analysis technique is the impossibility of associating capacitors with the resistive circuits. As the voltages are converted into pseudo-voltages, a linear capacitor in the ordinary voltage domain no longer behaves as such in the pseudo-voltage domain.
It would be desirable to have cells in the integrated circuits forming pseudo-capacitive components, for example of the C or RC type, the design of which would be suited to synthesis using pseudo-voltages, such cells enabling implementation of filters combining the spatial function with the temporal function, the latter being implemented using pseudo-capacitive components.
The aim of the invention is to provide an integrated circuit cell including a pseudo-capacitor showing linear behavior in the pseudo-voltage domain.